A system on a chip (SoC) cannot begin its startup process until the SoC receives a clock signal. During normal operation, a SoC typically receives its clock signal from a crystal oscillator. However, the startup time of a crystal oscillator is relatively slow, being on the order of milliseconds. So as to reduce total device startup time, an RC oscillator is typically used to provide a clock signal for the SoC to use during its startup process, as the startup time of the RC oscillator is relatively quick, on the order of microseconds.
A generic RC oscillator 50 for use for such purposes is now described with reference to FIG. 1. The RC oscillator 50 includes a SR flip flop 56 having a set input S, a reset input R, a non-inverting output Q, and an inverting output Qbar. Comparator 52 provides output to the set input S, while comparator 54 provides output to the reset input R.
A current generator 51 generates a bias current Ibias. Resistor R1 is coupled between the current generator 51 and the non-inverting input of the comparator 52, while resistor R2 is coupled between the current generator 51 and the non-inverting input of the comparator 54. A reference voltage Vref is coupled to the inverting inputs of the comparators 52 and 54. Capacitor C1 is coupled between the non-inverting input of the comparator 52 and ground, while capacitor C2 is coupled between the non-inverting input of the comparator 54 and ground. A switch S1 selectively shunts capacitor C1 to ground in response to assertion of the non-inverting output Q of the SR flip flop 56, while switch S2 selectively shunts capacitor C2 to ground in response to assertion of the inverting output Qbar of the flip flop 56.
In operation, assuming an initial condition of Q being low (and thus the clock CK generated by the RC oscillator 50 is low), Qbar would be high. Q being low opens switch S1 resulting in capacitor C1 being charged by the bias current Ibias, while Qbar being high results in switch S2 closing causing capacitor C2 to discharge to ground.
When the voltage across capacitor C1 rises to be equal to the reference voltage Vref, the comparator 52 will assert its output, causing the SR flip flop 56 to set, asserting Q and deasserting Qbar. This in turn causes switch S1 to close to discharge capacitor C1, and switch S2 to open to charge capacitor C2. When the voltage across capacitor C2 rises to be equal to Vref, the comparator 54 will assert its output, resetting the SR flip flop 56 to the state initially discussed.
This repeated operation yields a clock signal CK at the non-inverting output Q of the SR flip flop 56 that, provided the values of R1 and R2 are the same and the values of C1 and C2 are the same, is a square wave.
An issue arises if the SR flip flop 56 fails to transition when it should, due to errors caused by process variation in the formation of the components, for example. If this happens, the RC oscillator 50 becomes stuck, and ceases to generate the square wave, resulting in failure of startup operations of a SoC to which it is providing the clock signal CK.
Therefore, further development into the area of RC oscillators is needed so as to be able to detect these errors and correct them.